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EN5312QI
1A Synchronous Buck Regulator With Integrated Inductor
Revised March 2007
RoHS Compliant
Featuring Integrated Inductor Technology
VIN
Product Overview
The Ultra-Low-Profile EN5312QI is targeted to applications where board area and profile are critical. EN5312QI is a complete power conversion solution requiring only two low cost ceramic MLCC caps. Inductor, MOSFETS, PWM, and compensation are integrated into a tiny 5mm x 4mm x 1.1mm QFN package. The EN5312QI is engineered to simplify design and to minimize layout constraints. 4 MHz switching frequency and internal type III compensation provides superior transient response. With a 1.1 mm profile, the EN5312QI is ideal for space and height constrained applications. A 3-pin VID output voltage selector provides seven pre-programmed output voltages along with an option for external resistor divider. Output voltage can be programmed on-the-fly to provide fast, dynamic voltage scaling.
UVLO Thermal Limit Current Limit
ENABLE
Soft Start P-Drive (-) PWM Comp (+)
Logic
N-Drive
VOUT
GND Sawtooth Generator Compensation Network VSENSE
(-) Error Amp (+)
Switch VFB
DAC VREF Voltage Select Package Boundry VS0 VS1 VS2
Product Highlights
* Integrated Planar Inductor * Designed for low noise/low EMI * Very small solution foot print* * Only two low cost MLCC caps required * RoHS compliant; MSL 3 260C reflow * 5mm x 4mm x1.1mm QFN package * Wide 2.4V to 5.5V input range * 1000mA continuous output current * Less than 1 A standby current. * High efficiency, up to 95% * Excellent transient performance * Very low ripple voltage; 5mVp-p Typical * 3 Pin VID Output Voltage select * External divider: 0.6V to VIN-Vdropout * 4 MHz switching frequency * 100% duty cycle capable * Short circuit and over current protection * UVLO and thermal protection
Typical Application Circuit
ENABLE
VIN
4.7F
VSense
Vin
VOUT
10F
EN5312Q
Vout VFB
Voltage Select
VS0 VS1 VS2
GND
Figure 1. Typical application circuit.
Applications
* * * * * * * LDO replacement for improved thermals FPGA, DSP, ASIC, IO & Peripherals Area constrained applications Set top box/home gateway Smart phones and PDAs VoIP and Video phones Personal Media Players
*Optimized PCB Layout file downloadable from the Enpirion Website to assure first pass design success.
March 2007
EN5312QI
Pin Description
ENABLE
VS0
VS1
VS2
other or to any external signal, voltage, or ground. One or more of these pins may be connected internally.
VFB VSENSE NC NC NC NC
VIN VIN GND GND VOUT VOUT
1 2 3 4 5 6 10 7 8 9
16 15
VSENSE (Pin 15): Sense pin for output voltage regulation. Connect VSENSE to the output voltage rail as close to the terminal of the output filter capacitor as possible. VFB (Pin 16): Feed back pin for external divider option. When using the external divider option (VS0=VS1=VS2= high) connect this pin to the center of the external divider. Set the divider such that VFB = 0.603V. VS0,VS1,VS2 (Pin 17,18,19): Output voltage select. VS0=pin19, VS1=pin18, VS2=pin17. Selects one of seven preset output voltages or choose external divider by connecting pins to logic high or low. Logic low is defined as VLOW 0.4V. Logic high is defined as VHIGH 1.4V. Any level between these two values is indeterminate. ENABLE (Pin 20): Output enable. Enable = logic high, disable = logic low. Logic low is defined as VLOW 0.2V. Logic high is defined as VHIGH 1.4V. Any level between these two values is indeterminate. Bottom Thermal Pad: Device thermal pad to remove heat from package. Connect to PCB surface ground pad and PCB internal ground plane (see layout recommendations).
18
20
19
17 14 13 12 11
EN5312Q
Figure 2. Pin description, top view.
VIN (Pin 1,2): Input voltage pin. Supplies power to the IC. VIN can range from 2.4V to 5.5V. Input GND: (Pin 3): Input power ground. Connect this pin to the ground terminal of the input capacitor. Refer to Layout Recommendations for further details. Output GND: (Pin 4): Power ground. The output filter capacitor should be connected between this pin and VOUT. Refer to Layout recommendations for further detail. VOUT (Pin 5,6,7): Regulated output voltage. NC (Pin 8,9,10,11,12,13,14): These pins should not be electrically connected to each
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VOUT
NC
NC
NC
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EN5312QI
Functional Block Diagram
VIN
UVLO Thermal Limit Current Limit
ENABLE
Soft Start P-Drive (-) PWM Comp (+)
Logic
N-Drive
VOUT
GND Sawtooth Generator Compensation Network VSENSE
(-) Error Amp (+)
Switch VFB
DAC VREF Voltage Select Package Boundry VS0 VS1 VS2
Figure 3. Functional block diagram.
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EN5312QI
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond recommended operating conditions is not implied. Stress beyond absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. PARAMETER
Input Supply Voltage Voltages on: ENABLE, VSENSE, VS0-VS2 Voltage on: VFB Storage Temperature Range Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A ESD Rating (based on Human Body Model)
SYMBOL
VIN TSTG
MIN
-0.3 -0.3 -0.3 -65
MAX
7.0 VIN + 0.3 2.7 150 260 2000
UNITS
V V V C C V
Recommended Operating Conditions
PARAMETER
Input Voltage Range Output Voltage Range Output Current Operating Ambient Temperature Operating Junction Temperature
SYMBOL
VIN VOUT IOUT TA TJ
MIN
2.4 0.6 0 -40 -40
MAX
5.5 VIN-0.6 1000 +85 +125
UNITS
V V mA C C
Thermal Characteristics
PARAMETER
Thermal Resistance: Junction to Ambient (0 LFM) Thermal Resistance: Junction to Case (0 LFM) Thermal Shutdown Thermal Shutdown Hysteresis
SYMBOL
JA JC TJ-TP
TYP
65 15 +150 15
UNITS
C/W C/W C C
Electrical Characteristics
NOTE: TA = 25C unless otherwise noted. Typical values are at VIN = 3.6V, CIN = 4.7F, COUT=10uF. NOTE: VIN must be greater than VOUT + 0.6V. PARAMETER Operating Input Voltage Under Voltage Lockout UVLO Hysteresis Output Voltage with VID Preset Codes. NOTE: VS Pins must not be left floating VOUT
SYMBOL
TEST CONDITIONS VIN going low to high
VIN VUVLO
MIN 2.4
TYP 2.2 0.145
MAX 5.5 2.3
UNITS V V V
2.4V VIN 5.5V, ILOAD = 100mA VS2 VS1 VS0 VOUT(V) 0 0 0 3.3 0 0 1 2.5 0 1 0 1.8 0 1 1 1.5 1 0 0 1.25 1 0 1 1.2 1 1 0 0.8 2.4V VIN 5.5V, ILOAD = 100mA
-2.0 -2.0 -2.0 -2.0 -2.0 -2.0 -2.0 0.591 0.603
+2.0 +2.0 +2.0 +2.0 +2.0 +2.0 +2.0 0.615
%
Feedback Pin Voltage
VFB
V
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PARAMETER Feedback Pin Input Current Output Voltage with VID Preset Codes. NOTE: VS Pins must not be left floating VOUT
SYMBOL
EN5312QI
TEST CONDITIONS VSO=VS1=VS2=1 MIN TYP 1 2.4V VIN 5.5V, ILOAD = 0 - 1A, TA = -40C to +85C VS2 VS1 VS0 VOUT(V) 0 0 0 3.3 0 0 1 2.5 0 1 0 1.8 0 1 1 1.5 1 0 0 1.25 1 0 1 1.2 1 1 0 0.8 2.4V VIN 5.5V, ILOAD = 0 - 1A, TA = -40C to +85C VSO=VS1=VS2=1 2.4V VIN 5.5V 0A ILOAD 1A MAX UNITS nA IFB
-3.0 -3.0 -3.0 -3.0 -3.0 -3.0 -3.0
+3.0 +3.0 +3.0 +3.0 +3.0 +3.0 +3.0
%
Feedback Pin Voltage Line Regulation Load Regulation Dynamic Voltage Slew Rate Output Current Shut-Down Current Quiescent Current PFET OCP Threshold VS0-VS1 Thresholds VS0-VS2 Pin Input Current Enable Voltage Threshold Enable Pin Input Current Operating Frequency PFET On Resistance NFET On Resistance Typical inductor DCR Soft-Start Operation Time to 90% Vout
VFB
0.585
0.603 .05 .0003 1.65
0.621
V %/V %/mA V/mS mA A A A
Vslew IOUT ISD ILIM VTH IVSX IEN FOSC RDS(ON) RDS(ON)
1000 Enable = Low No switching 2.4V VIN 5.5V, 0.6V VOUT VIN - 0.6V Pin = Low Pin = High Logic Low Logic High VIN = 3.6V 0.75 800 1.4 0.0 1.4 1 0.0 1.4 2 4 340 270 .110 2 0.2 VIN 2 0.4 VIN
nA V A MHz m m mS
Tss
Vout = 3.3V
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EN5312QI
Typical Performance Characteristics
Efficiency vs Output Current
100 90 80 70 Efficiency -% 60 50 40 30 20 10 0 50 150 250 350 450 550 650 750 850 950
Efficiency vs Output Current
100 95
V IN = 3.3V
V IN = 5.0V
90
Efficiency -%
85 80 75 70 65 60
VIN = 5.0V V IN = 3.6V
V OUT = 3.3V
55 50 50 150 250 350 450 550 650
V OUT = 2.5V
750 850 950
Load Current (mA)
Load Current (mA)
Efficiency vs Output Current
100 95 90
Start up Waveform
V IN = 2.5V
E fficiency -%
85 80 75 70 65 60 55 50 50 150 250 350 450 550 650 750 850 950
Vout 1V/Div
VIN = 5.0V V IN = 3.6V
V IN = 3.3V
V OUT = 1.8V
Enable 1V/Div VIN = 5.0V VOUT = 3.3V 400s/Div
Load Current (mA)
Transient Response
Transient Response
Vout 50mV/Div
Vout 50mV/Div
ILoad 500mA/Div VIN = 5.0V 20s/Div VOUT = 3.3V Iload = 100mA to 800mA
ILoad 500mA/Div VIN = 3.3V 20s/Div VOUT = 1.8V Iload = 100mA to 800mA
Output Ripple
Output Ripple
V out 10mV/Div
V out 10mV/Div
VIN = 5.0V 200ns/Div VOUT = 3.3V Output Cap = 10 F 0805
V IN = 5.0V 200ns/Div V OUT = 3.3V Output Cap = 2 x 10 F 0805
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EN5312QI short circuit protection, and thermal overload protection.
Detailed Description
Functional Overview
The EN5312QI is a complete DCDC converter solution requiring only two low cost MLCC capacitors. MOSFET switches, PWM controller, Gate-drive, compensation, and inductor are integrated into the tiny 5mm x 4mm x 1.1mm package to provide the smallest footprint possible while maintaining high efficiency, low ripple, and high performance. The converter uses voltage mode control to provide the simplest implementation and high noise immunity. The device operates at a high switching frequency. The high switching frequency allows for a wide control loop bandwidth providing excellent transient performance. The high switching frequency enables the use of very small components making possible this unprecedented level of integration. Enpirion's proprietary power MOSFET technology provides very low switching loss at frequencies of 4 MHz and higher, allowing for the use of very small internal components, and very wide control loop bandwidth. Unique magnetic design allows for integration of the inductor into the very low profile 1.1mm package. Integration of the inductor virtually eliminates the design/layout issues normally associated with switch-mode DCDC converters. All of this enables much easier and faster integration into various applications to meet demanding EMI requirements. Output voltage is chosen from seven preset values via a three pin VID voltage select scheme. An external divider option enables the selection of any voltage in the 0.6V to VIN0.6V range. This reduces the number of components that must be qualified and reduces inventory burden. The VID pins can be toggled on the fly to implement glitch free dynamic voltage scaling. Protection features include under-voltage lockout (UVLO), over-current protection (OCP),
(c)Enpirion 2007 all rights reserved, E&OE
Integrated Inductor
Enpirion has introduced the world's first product family featuring integrated inductors. The EN5312QI utilizes a low loss, planar construction inductor. The use of an internal inductor localizes the noises associated with the output loop currents. The inherent shielding and compact construction of the integrated inductor reduces the radiated noise that couples into the traces of the circuit board. Further, the package layout is optimized to reduce the electrical path length for the AC ripple currents that are a major source of radiated emissions from DCDC converters. The integrated inductor significantly reduces parasitic effects that can harm loop stability, and makes layout very simple.
Soft Start
Internal soft start circuits limit in-rush current when the device starts up from a power down condition or when the "ENABLE" pin is asserted "high". Digital control circuitry limits the VOUT ramp rate to levels that are safe for the Power MOSFETS and the integrated inductor. The soft start ramp rate is nominally 1.65V/mS.
Over Current/Short Circuit Protection
The current limit function is achieved by sensing the current flowing through a sense PMOSFET which is compared to a reference current. When this level is exceeded the PFET is turned off and the N-FET is turned on, pulling VOUT low. This condition is maintained for a period of 1mS and then a normal soft start is initiated. If the over current condition still persists, this cycle will repeat in a "hick-up" mode.
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Under Voltage Lockout
During initial power up an under voltage lockout circuit will hold-off the switching circuitry until the input voltage reaches a sufficient level to insure proper operation. If the voltage drops below the UVLO threshold the lockout circuitry will again disable the switching. Hysteresis is included to prevent chattering between states.
EN5312QI enable the converter into normal operation. In shutdown mode, the device quiescent current will be less than 1 uA. NOTE: This pin must not be left floating.
Thermal Shutdown
When excessive power is dissipated in the chip, the junction temperature rises. Once the junction temperature exceeds the thermal shutdown temperature the thermal shutdown circuit turns off the converter output voltage thus allowing the device to cool. When the junction temperature decreases by 15C, the device will go through the normal startup process.
Enable
The ENABLE pin provides a means to shut down the converter or enable normal operation. A logic low will disable the converter and cause it to shut down. A logic high will
Application Information
Output Voltage Select
To provide the highest degree of flexibility in choosing output voltage, the EN5312QI uses a 3 pin VID, or Voltage ID, output voltage select arrangement. This allows the designer to choose one of seven preset voltages, or to use an external voltage divider. Internally, the output of the VID multiplexer sets the value for the voltage reference DAC, which in turn is connected to the non-inverting input of the error amplifier. This allows the use of a single feedback divider with constant loop gain and optimum compensation, independent of the output voltage selected. Table 1 shows the various VS0-VS2 pin logic states and the associated output voltage levels. A logic "1" indicates a connection to VIN or to a "high" logic voltage level. A logic "0" indicates a connection to ground or to a "low" logic voltage level. These pins can be either hardwired to VIN or GND or alternatively can be driven by standard logic levels. Logic low is defined as VLOW 0.4V. Logic high is defined as VHIGH 1.4V. Any level between these two values is indeterminate. These pins must not be left floating.
Table 1. VID voltage select settings.
VS2 0 0 0 0 1 1 1 1
VS1 0 0 1 1 0 0 1 1
VS0 0 1 0 1 0 1 0 1
VOUT
3.3V 2.5V 1.8V 1.5V 1.25V 1.2V 0.8V User Selectable
External Voltage Divider
As described above, the external voltage divider option is chosen by connecting the VS0, VS1, and VS2 pins to VIN or logic "high". The EN5312QI uses a separate feedback pin, VFB, when using the external divider. VSENSE must be connected to VOUT as indicated in Figure 4.
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ENABLE
VIN
4.7uF
VSense Vout Ra VFB Rb GND 10F
Vin
VOUT
VS0 VS1 VS2
EN5312QI formulation. Y5V or equivalent dielectric formulations lose capacitance with frequency, bias, and with temperature, and are not suitable for switch-mode DC-DC converter input and output filter applications. The output capacitance requirement is a minimum of 10uF. The control loop is designed to be stable with up to 60uF of total output capacitance without requiring modification to the compensation network. Capacitance above the 10uF minimum should be added if the transient performance is not sufficient using the 10uF. Enpirion recommends a low ESR MLCC type capacitor be used. The output capacitor must use a X5R or X7R or equivalent dielectric formulation. Y5V or equivalent dielectric formulations lose capacitance with frequency, bias, and temperature and are not suitable for switchmode DC-DC converter input and output filter applications.
Cin Manufacturer Murata Part # GRM219R61A475KE19D GRM319R61A475KA01D GRM219R60J475KE01D GRM31MR60J475KA01L ECJ-2FB1A475K ECJ-3YB1A475K ECJ-2FB0J475K ECJ-3YB0J475K LMK212BJ475KG-T LMK316BJ475KD-T JMK212BJ475KD-T
Part # GRM219R60J106KE19D GRM319R60J106KE01D ECJ-2FB0J106K ECJ-3YB0J106K JMK212BJ106KD-T JMK316BJ106KF-T
Figure 4. External Divider.
The output voltage is selected by the following formula: VOUT = 0.603V (1 +
Ra Rb
)
Ra must be chosen as 200K to maintain loop gain. Then Rb is given as:
EN5312
Rb =
1.2 x10 5 VOUT - 0.603
VOUT can be programmed over the range of 0.6V to VIN - 0.6V (0.6 is the nominal full load dropout voltage including margin).
Dynamically Adjustable Output
The EN5312QI is designed to allow for dynamic switching between the predefined VID voltage levels The inter-voltage slew rate is optimized to prevent excess undershoot or overshoot as the output voltage levels transition. The slew rate is identical to the softstart slew rate of 1.65V/mS. Dynamic transitioning between internal VID settings and the external divider is not allowed.
Value 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF
Value 10uF 10uF 10uF 10uF 10uF 10uF
WVDC 10V 10V 10V 10V 10V 10V 6.3V 6.3V 10V 10V 6.3V
WVDC 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
Case Size 0805 1206 0805 1206 0805 1206 0805 1206 0805 1206 0805
Case Size 0805 1206 0805 1206 0805 1206
Panasonic
Taiyo Yuden
Cout Manufacturer Murata
Input and Output Capacitors
The input capacitance requirement is 4.7uF. Enpirion recommends that a low ESR MLCC capacitor be used. The input capacitor must use a X5R or X7R or equivalent dielectric
Panasonic
Taiyo Yuden
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EN5312QI
LAYOUT CONSIDERATIONS*
*Optimized PCB Layout file downloadable from the Enpirion Website to assure first pass design success.
Recommendation 1: Input and output filter capacitors should be placed as close to the EN5312QI package as possible to reduce EMI from input and output loop AC currents. This reduces the physical area of the Input and Output AC current loops. Recommendation 2: DO NOT connect GND pins 3 and 4 together. Pin 3 should be used for the Input capacitor local ground and pin 4 should be used for the output capacitor ground. The ground pad for the input and output filter capacitors should be isolated ground islands and should be connected to system ground as indicated in recommendation 3 and recommendation 5. Recommendation 3: Multiple small vias (0.25mm after copper plating) should be used to connect ground terminals of the Input capacitor and the output capacitor to the system ground plane. This provides a low inductance path for the high-frequency AC currents, thereby reducing ripple and suppressing EMI (see Fig. 5, Fig. 6, and Fig. 7). Recommendation 4: The large thermal pad underneath the component must be connected to the system ground plane through as many thermal vias as possible. The vias should use 0.33mm drill size with minimum one ounce copper plating (0.035mm plating thickness). This provides the path for heat dissipation from the converter. Recommendation 5: The system ground plane referred to in recommendations 3 and 4 should be the first layer immediately below the surface layer (PCB layer 2). This ground plane should be continuous and un-interrupted below the converter and the input and output capacitors that carry large AC currents. If it is not possible to make PCB layer 2 a continuous ground plane, an uninterrupted ground "island" should be created on PCB layer 2 immediately underneath the EN5312QI and its input and output capacitors. The vias that connect the input and output capacitor grounds, and the thermal pad to the ground island, should continue through to the PCB GND layer as well. Recommendation 6: As with any switch-mode DC/DC converter, do not run sensitive signal or control lines underneath the converter package. Figure 5 shows an example schematic for the EN5312QI using the internal voltage select. In this example, the device is set to a VOUT of 1.5V (VS2=0, VS1=1, VS0=1).
VSENSE NC NC NC NC
VSENSE
VFB
VFB
NC
12
NC
16
15
14
13
12
11
16
15
14
13
NC
VS2 VS1 VS0 ENABLE
17 18 19 20 5 1 2 3 4 6
10 9 8 7
NC NC NC VOUT
11
NC
10 9 8 7
VS2 VS1 VS0 ENABLE
17 18 19 20 5 1 2 3 4 6
NC NC NC VOUT
Rb=60K
Ra=200K
GND
GND
GND
GND
VOUT
VOUT
VOUT
VOUT
VOUT
VIN
VIN
VIN
VIN
VIN
4.7uF 10F
VIN
4.7uF 10F
VOUT
(see layout recommendation 3)
(see layout recommendation 3)
Figure 5. Example application, Vout=1.5V. (c)Enpirion 2007 all rights reserved, E&OE
Figure 6. Example Application, external divider, Vout = 2.6V.
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March 2007 EN5312QI Figure 6 shows an example schematic using an external voltage divider. VS0=VS1=VS2= "1". The resistor values are chosen to give an output voltage of 2.6V. Figure 7 shows an example board layout. The left side of the figure demonstrates construction of the PCB top layer. Note the placement of the vias from the input and output filter capacitor grounds, and the thermal pad, to the PCB ground on layer 2 (1st layer below PCB surface). The right side of the figure shows the layout with the components populated. Note the placement of the vias per recommendation 3.
Thermal Vias to Ground Plane
Package Outline
CIN
COUT
Vias to Ground Plane Ground
Figure 7. Example layout showing PCB top layer, as well as demonstrating use of vias from input, output filter capacitor local grounds, and thermal pad, to PCB system ground.
Design Considerations for Lead-Frame Based Modules
Exposed Metal on Bottom Of Package
Enpirion has developed a break-through in package technology that utilizes the lead frame as part of the electrical circuit. The lead frame offers many advantages in thermal performance, in reduced electrical lead resistance, and in overall foot print. However, it does require some special considerations. As part of the package assembly process, lead frame construction requires that for mechanical support, some of the lead-frame cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several small pads being exposed on the bottom of the package. Only the large thermal pad and the perimeter pin pads are to be mechanically or electrically connected to the PC board. The PCB top layer under the EN5312QI should be clear of any metal except for the large thermal pad. The "grayed-out" area in Figure 8 represents the area that should be clear of any metal (traces, vias, or planes), on the top layer of the PCB. NOTE: Clearance between the various exposed metal pads, the thermal ground pad, and the perimeter pins, meets or exceeds JEDEC requirements for lead frame package construction (JEDEC MO-220, Issue J, Date May 2005). The separation between the large thermal pad and the nearest adjacent metal pad or pin is a minimum of 0.20mm, including tolerances. This is shown in Figure 9.
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EN5312QI
Thermal Pad. Connect to Ground plane
Figure 8. Exposed metal and mechanical dimensions of the package. Gray area represents bottom metal noconnect and area that should be clear of any traces, planes, or vias, on the top layer of the PCB.
0.25
0.25
0.20
0.20
0.20
JEDEC minimum separation = 0.20
Figure 9. Exposed pad clearances; the Enpirion lead frame package complies with JEDEC requirements.
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EN5312QI
Figure 10. Recommended solder mask opening.
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EN5312QI
Figure 11. Package mechanical dimensions.
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EN5312QI
Tape & Reel Specification
Figure 12. Tape and reel mechanical dimensions.
Ordering Information
Part Number
EN5312QI-T EN5312QI-E
Temp Range
-40C to +85C
Package
QFN20 Evaluation Board Tape & Reel
Additional Products
Part Number
EP5352QI EP5362QI EP5382QI EQ5352DI EQ5362DI EQ5382DI EN5335QI EN5336QI EN5365QI EN5366QI
Description
500mA DCDC with integrated inductor; 5mmx4mmx1.1mm package 600mA DCDC with integrated inductor; 5mmx4mmx1.1mm package 800mA DCDC with integrated inductor; 5mmx4mmx1.1mm package 500mA DCDC regulator; tiny 3mm x2mm x0.9mm DFN package 600mA DCDC regulator; tiny 3mm x2mm x0.9mm DFN package 800mA DCDC regulator; tiny 3mm x2mm x0.9mm DFN package 3A DCDC with integrated inductor; 10mm x 7.5mm x 1.85mm QFN package 3-Pin VID VOUT programming 3A DCDC with integrated inductor; 10mm x 7.5mm x 1.85mm QFN package External resistor divider VOUT programming 6A DCDC with integrated inductor; 12mm x 10mm x 1.85mm QFN package 3-Pin VID VOUT programming; Parallel Capable 6A DCDC with integrated inductor; 12mm x 10mm x 1.85mm QFN package External resistor divider VOUT programming; Parallel Capable
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EN5312QI
Contact Information
Enpirion, Inc. 685 US Route 202/206 Suite 305 Bridgewater, NJ 08807 Phone: +1 908-575-7550 Fax: +1 908-575-0775 www.enpirion.com
Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment used in hazardous environment without the express written authority from Enpirion.
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